general description the mxd1210 nonvolatile ram controller is a very low- power cmos circuit that converts standard (volatile) cmos ram into nonvolatile memory. it also continually monitors the power supply to provide ram write protec- tion when power to the ram is in a marginal (out-of-tol- erance) condition. when the power supply begins to fail, the ram is write-protected, and the device switch- es to battery-backup mode. applications microprocessor systems computers embedded systems features ? battery backup ? memory write protection ? 230? operating mode quiescent current ? 2na backup mode quiescent current ? battery freshness seal ? optional redundant battery ? low forward-voltage drop on v cc supply switch ? 5% or 10% power-fail detection options ? tests battery condition during power-up ? 8-pin so available mxd1210 nonvolatile ram controller ________________________________________________________________ maxim integrated products 1 8 v cci +5v 1 2 7 vbatt2 6 3 5 4 gnd ce v cc cmos ram mxd1210 ce from decoder vbatt1 v cco part temp range pin-package MXD1210C/d 0? to +70? dice* MXD1210Cpa 0? to +70? 8 pdip MXD1210Csa 0? to +70? 8 so MXD1210Cwe 0? to +70? 16 wide so mxd1210epa -40? to +85? 8 pdip mxd1210esa -40? to +85? 8 so mxd1210ewe -40? to +85? 16 wide so mxd1210mja -55? to +125? 8 cerdip typical operating circuit ordering information ceo ce gnd 1 2 8 7 v cci vbatt2 vbatt1 tol v cco dip/so top view 3 4 6 5 mxd1210 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 n.c. n.c. v cci n.c. vbatt2 n.c. ceo n.c. ce mxd1210 wide so v cco n.c. tol vbatt1 n.c. n.c. gnd pin configurations 19-0154; rev 2; 11/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * contact factory for dice specifications. devices in pdip and so packages are available in both lead- ed and lead-free packaging. specify lead free by adding the + symbol at the end of the part number when ordering. lead free not available for cerdip package.
mxd1210 nonvolatile ram controller 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cci to gnd ..........................................................-0.3v to +7.0v vbatt1 to gnd.....................................................-0.3v to +7.0v vbatt2 to gnd.....................................................-0.3v to +7.0v v cco to gnd ................................................-0.3v to (v s + 0.3v) (v s = greater of v cci , vbatt1, vbatt2) digital input and output voltages to gnd.....................................-0.3v to (v cci + 0.3v) continuous power dissipation (t a = +70?) 8-pin pdip (derate 9.09mw/? above +70?)..............727mw 8-pin so (derate 5.88mw/? above +70?).................471mw 8-pin cerdip (derate 8.00mw/? above +70?).........640mw 16-pin wide so (derate 9.52mw/? above +70?) .....762mw operating temperature range c suffix.................................................................0? to +70? e suffix ..............................................................-40? to +85? m suffix ...........................................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units tol = gnd 4.75 5.50 supply voltage v cci tol = v cco 4.50 5.50 v input high voltage v ih 2.2 v input low voltage v il 0.8 v battery voltage vbatt1 vbatt2 1 or 2 batteries (note 1) 2.0 4.0 v electrical characteristics?ormal supply mode, tol = v cco (v cci = +4.75v to +5.5v, tol = gnd; or v cci = +4.5v to +5.5v, tol = v cco ; t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units supply current i cci v cco , ceo open, vbatt1 = vbatt2 = 3v 0.23 0.5 ma MXD1210C v cci - 0.20 mxd1210e v cci - 0.21 output supply voltage v cco i cco1 = 80ma (note 2) mxd1210m v cci - 0.25 v MXD1210C 80 mxd1210e 0.23 75 output supply current i cco v cci - v cco 0.2v (note 2) mxd1210m 0.23 65 ma input leakage current i il ?.0 a output leakage current i ol ?.0 a high-level output voltage v oh i oh = -1ma 2.4 v low-level output voltage v ol i ol = 4ma 0.4 v tol = gnd 4.50 4.74 v cci trip point v cctp tol = v cco 4.25 4.49 v
mxd1210 nonvolatile ram controller _______________________________________________________________________________________ 3 note 1: only one battery input is required. unused battery inputs must be grounded. note 2: i cco1 is the maximum average load current the mxd1210 can supply to the memories. note 3: i cco2 is the maximum average load current the mxd1210 can supply to the memories in battery-backup mode. note 4: ceo can sustain leakage current only in battery-backup mode. note 5: guaranteed by design. note 6: t ce max must be met to ensure data integrity on power loss. electrical characteristics?attery-backup mode (v cci < v batt , positive edge rate at vbatt1, vbatt2 > 0.1v/?, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units MXD1210C/e 2 100 na quiescent current (note 1) i batt v cco , ceo open, v cci = 0v mxd1210m 5 a output supply current i cco2 v batt - v cco 0.2v (notes 3, 4) 300 ? ceo output voltage v o output open v batt - 0.2 v capacitance (t a = t min to t max , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units input capacitance c in 5pf output capacitance c out 7pf v cc power timing characteristics (v cci = +4.75v to +5.5v, tol = gnd; or v cci = +4.5v to +5.5v, tol = v cco , t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units MXD1210C 5 10 20 mxd1210e 5 10 22 ce propagation delay t pd r l = 1k , c l = 50pf mxd1210m 5 10 25 ns ce high to power-fail t pf (note 5) 0 ns timing characteristics (v cci < +4.75v to +5.5v, tol = gnd; or v cci < +4.5v, tol = v cco , t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units recovery at power-up t rec 2520ms t f to out-of-tolerance condition 300 v cc slew-rate power-down t fb tolerance to battery power 10 ? v cc slew-rate power-up t r 0 s ce pulse width t ce (note 6) 1.5 ?
mxd1210 nonvolatile ram controller 4 _______________________________________________________________________________________ 4 _______________________________________________________________________________________ pin description pin 8-pin pdip/so 16-pin wide so name function 12v cco backed-up supply to ram 2 4 vbatt1 battery 1 positive connection 3 6 tol tolerance select pin 4 8 gnd ground 59 ce chip-enable input 611 ceo chip-enable output 7 13 vbatt2 battery 2 positive connection 815v cci 5v power supply to chip 1, 3, 5, 7, 10, 12, 14, 16 n.c. no connection. not internally connected. v cci v cco gnd ceo gnd p p p p freshness- seal mode voltage level detection battery test battery select ceo control n vbatt1 vbatt2 ce tol mxd1210 figure 1. block diagram
mxd1210 nonvolatile ram controller _______________________________________________________________________________________ 5 _______________________________________________________________________________________ 5 detailed description main functions the mxd1210 executes five main functions to perform reliable ram operation and battery backup (see the typical operating circuit and figure 1): 1) ram power-supply switch: the switch directs power to the ram from the incoming supply or from the selected battery, whichever is at the greater voltage. the switch control uses the same criterion to direct power to mxd1210 internal cir- cuitry. 2) power-failure detection: the write-protection function is enabled when a power failure is detected. the power-failure detection range depends on the state of the tol pin as follows: power-failure detection is independent of the bat- tery-backup function and precedes it sequentially as the power-supply voltage drops during a typi- cal power failure. 3) write protection: this holds the chip-enable out- put ( ceo ) to within 0.2v of v cci or of the selected battery, whichever is greater. if the chip-enable input ( ce ) is low (active) when power failure is detected, then ceo is held low until ce is brought high, at which time ceo is gated high for the duration of the power failure. the preceding sequence completes the current rd/wr cycle, preventing data corruption if the ram access is a wr cycle. 4) battery redundancy: a second battery is option- al. when two batteries are connected, the stronger battery is selected to provide ram back- up and to power the mxd1210. the battery-selec- tion circuitry remains active while in the battery-backup mode, selecting the stronger bat- tery and isolating the weaker one. the battery- selection activity is transparent to the user and the system. if only one battery is connected, the second battery input should be grounded. 5) battery-status warning: this notifies the system when the stronger of the two batteries measures 2.0v. each time the mxd1210 is repowered (v cci > v cctp ) after detecting a power failure, the bat- tery voltage is measured. if the battery in use is low, following the mxd1210 recovery period, the device issues a warning to the system by inhibit- ing the second memory cycle. the sequence is as follows: first access: read memory location n, loc(n) = x second access: write memory location n, loc(n) = complement (x) third access: read memory location n, loc(n) = ? if the third access (read) is complement (x), then the battery is good; otherwise the battery is not good. return to loc(n) = x following the test sequence. freshness-seal mode the freshness-seal mode relates to battery longevity during storage rather than directly to battery backup. this mode is activated when the first battery is con- nected, and is defeated when the voltage at v cci first exceeds v cctp . in the freshness-seal mode, both bat- teries are isolated from the system; that is, no current is drained from either battery, and the ram is not pow- ered by either battery. this means that batteries can be installed and the system can be held in inventory with- out battery discharge. the positive edge rate at vbatt1 and vbatt2 should exceed 0.1v/?. the bat- teries will maintain their full shelf life while installed in the system. battery backup the typical operating circuit shows the mxd1210 con- nected to write-protect the ram when v cc is less than 4.75v, and to provide battery backup to the supply. condition v cctp range (v) tol = gnd 4.75 to 4.50 tol = v cco 4.50 to 4.25
mxd1210 nonvolatile ram controller 6 _______________________________________________________________________________________ v ih v ih t pd t r t rec v batt - 0.2v v cci ceo ce 4.75v 4.5v 4.25v figure 2. power-up timing diagram v ih v ih v il v il t ce t ce t fb t pf t f t pd v cci ceo ce 4.75v 4.5v 4.25v 3v v batt - 0.2v figure 3. power-down timing diagram
mxd1210 nonvolatile ram controller _______________________________________________________________________________________ 7 chip topography vbatt1 v cco tol 0.121" (3.073mm) 0.080" (2.032mm) v cci vbatt2 ceo gnd ce transistor count: 1436; leave substrate unconnected.
mxd1210 nonvolatile ram controller 8 _______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0 -8 l 1 variations:
mxd1210 nonvolatile ram controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) pdipn.eps
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